The present invention relates generally to integrated circuits and in particular the present invention relates high voltage regulators and voltage reduction circuits utilized in low voltage integrated circuits.
Most integrated circuits and memory devices are designed to operate using a specific voltage power supply, such as 5Vxc2x110%, that their internal process technologies are designed to tolerate. In modem integrated circuits and memories, the need for higher voltage power supplies is reduced as the process feature sizes, such as transistors, are reduced and operating speeds increase. However, in many situations the externally supplied high voltage is fixed by past usage, convention, or industry specification and is unable to be easily reduced to for the lower voltage tolerant process technologies.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called xe2x80x9cerase blocksxe2x80x9d. Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation. For ease of access and management the erase blocks of a non-volatile memory device are typically arranged in xe2x80x9cbanksxe2x80x9d or segments.
Both RAM and ROM random access memory devices have memory cells that are typically arranged in an array of rows and columns. During operation, a row (page) is accessed and then memory cells can be randomly accessed on the page by providing column addresses. FIG. 1 shows a simplified diagram of a system 128 incorporating a Flash memory 100 of the prior art coupled to a processing device or controller 102. The Flash memory 100 has an address interface 104, a control interface 106, and a data interface 108 that are each coupled to the processing device 102 to allow memory read and write accesses. Internally to the Flash memory device a control state machine 110 directs internal operation of the Flash memory device; managing the Flash memory array 112 and updating RAM control registers and non-volatile erase block management registers 114. The RAM control registers and tables 114 are utilized by the control state machine 110 during operation of the Flash memory 100. The Flash memory array 112 contains a sequence of memory banks or segments 116. Each bank 116 is organized logically into a series of erase blocks (not shown). Memory access addresses are received on the address interface 104 of the Flash memory 100 and divided into a row and column address portions. On a read access the row address is latched and decoded by row decode circuit 120, which selects and activates a row page (not shown) of memory cells across a selected memory bank. The bit values encoded in the output of the selected row of memory cells are coupled from a local bitline (not shown) to a global bitline (not shown) and detected by sense amplifiers 122 associated with the memory bank. The column address of the access is latched and decoded by the column decode circuit 124. The output of the column decode circuit selects the desired column data from the sense amplifier outputs and coupled to the data buffer 126 for transfer from the memory device through the data interface 108. On a write access the row decode circuit 120 selects the row page and column decode circuit selects write sense amplifiers 122. In programming a Flash memory, a charge pump circuit 130 is first activated to provide a higher programming voltage to the floating gate memory cells of the memory array 112 than the voltage supplied to operate the memory 100. Data values to be written are coupled from the data buffer 126 to the write sense amplifiers 122 selected by the column decode circuit 124 and written to the selected floating gate memory cells (not shown) of the memory array 112. The written cells are then reselected by the row and column decode circuits 120, 124 and sense amplifiers 122 so that they can be read to verify that the correct values have been programmed into the selected memory cells.
Many Flash memories support fast or xe2x80x9cfactoryxe2x80x9d programming wherein the Flash memory is rapidly programmed with data. Instead of the internal charge pump, the factory programming mode typically utilizes an exterior high voltage power source that is more capable of supplying the power and current demanded in rapid programming. This external high voltage input is typically reduced and regulated for internal use by a regulator circuit the Flash memory. In addition to Flash memories, many other integrated circuits and memories utilize such an external high voltage input and regulator for internal operations. A problem with external high voltage input in integrated circuits is that the modern process technologies are in many cases unable to tolerate the field or voltage level of the external high voltage input. Additionally, as stated above, in many situations the externally supplied high voltage is fixed by past usage, convention, or industry specification and cannot be easily altered by the integrated circuit designer.
One such manner of operating a voltage regulator off an input voltage that is higher than the process breakdown voltage level is by the utilization of a voltage reduction circuit which utilizes what is termed xe2x80x9cback biasxe2x80x9d. In voltage reduction circuits utilizing back bias, an input MOS transistor(s) that is coupled to the external input voltage is formed in one or more separate isolation wells, isolated from the rest of the integrated circuit. Isolation wells are electrically isolated wells created by forming a well of oppositely doped silicon in the bulk material that, in turn, contains an area of silicon that is doped the same as the bulk, (i.e., a N-doped well in a P-doped bulk, containing a P-doped well material) creating an inherent reversed biased PN diode junction that isolates the circuits formed in the well. The input transistors are xe2x80x9cdiode connectedxe2x80x9d with the gate coupled to the drain so that they operate as a two terminal device in the threshold region and drop a threshold value of voltage potential. The bulk material inside the isolation wells is coupled to the source of the input transistor(s) so that the voltage across the transistor(s) of the voltage reduction circuit formed in the isolation well(s) is generally only a threshold drop and well within the process limits of the transistor(s). One or more voltage reduction transistors in on or more isolation wells can be serially coupled to produce a larger voltage reduction. In this manner existing process steps can be utilized to handle an external input voltage that is higher than the process technology limits are without additional special or expensive process steps.
Voltage reduction circuits that utilize drain coupled back bias can suffer from reduced current flow because of the limited voltage available for generating the conducting carrier channel in the MOS transistor. With source coupled back bias only a threshold drop of potential is applied to the gate/bulk of the transistor to generate the conduction channel. This can restrict the final voltage and current flow available to be utilized and/or regulated by the integrated circuit. Also, the application of a rigidly fixed back bias cannot easily be adjusted for circuit needs and input voltages and/or reduce the available voltage for regulation. An additional problem can be the size requirements of a voltage reduction circuit with multiple isolation wells. A further issue is the possibility of a reverse bias condition when the external voltage input is pulled to ground and a voltage is being applied to the isolation well through the back bias/voltage regulator connection. In this situation it is possible for the inherent PN diode junctions of the MOS transistor""s source/drain to forward bias and source current into the grounded external voltage connection.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, that there is a need in the art for an improved voltage reduction circuit and voltage regulator for low voltage process integrated circuits and memories.
The above-mentioned problems with high voltage reduction and regulation for low voltage process integrated circuits and memories are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a voltage reduction circuit comprises an isolation well containing one or more serially coupled metal oxide semiconductor (MOS) transistors, wherein each MOS transistor has its gate coupled to its drain to operate in diode coupled mode and wherein a first MOS transistor of the one or more serially coupled MOS transistors is coupled to an external voltage input, and a back bias control circuit to apply a back bias voltage to the isolation well.
In another embodiment, a voltage regulator circuit comprises a voltage reduction circuit coupled to an external input, a back bias control circuit coupled to the voltage reduction circuit, and a voltage regulation circuit coupled to the voltage reduction circuit.
In yet another embodiment, a back bias control circuit comprises one or more serially coupled input resistors, wherein each input resistor is formed in an isolation well and wherein a first input resistor is coupled to an external voltage input, one or more serially coupled output resistors, wherein each output resistor is formed in an isolation well and a final output resistor is coupled to a lower power rail, and a schmitt trigger coupled to a final input resistor of the one or more serially coupled input resistors and to a first output resistor of the one or more serially coupled output resistors, wherein the schmitt trigger selectively enables and disables at a predetermined voltage threshold value of the external voltage input.
In a further embodiment, a Flash memory device comprises a memory array containing a plurality of floating gate memory cells, an address interface coupled to a row address decoder and a column address decoder, a control circuit coupled to the memory array and the address interface, and a voltage regulator circuit, wherein the voltage regulator circuit is coupled an external voltage input and the memory array and is adapted to provide a programming current and a programming voltage when the Flash memory device operates in fast programming mode and wherein the voltage regulator circuit comprises a voltage reduction circuit, a back bias control circuit, and a voltage regulation circuit.
In yet a further embodiment, a system comprises a processor, and a Flash memory device coupled to the processor, wherein the Flash memory device comprises a memory array containing a plurality of floating gate memory cells, an address interface coupled to a row address decoder and a column address decoder, a control circuit coupled to the memory array and the address interface, and a voltage regulator circuit, wherein the voltage regulator circuit is coupled an external voltage input and the memory array and is adapted to provide a programming current and a programming voltage when the Flash memory device operates in fast programming mode and wherein the voltage regulator circuit comprises a voltage reduction circuit a back bias control circuit, and a voltage regulation circuit.
In another embodiment, an integrated circuit comprises a voltage reduction circuit coupled to an external input, a back bias control circuit coupled to the voltage reduction circuit, and a voltage regulation circuit coupled to the voltage reduction circuit.
In yet another embodiment, a method of operating a voltage reduction circuit comprises receiving an external voltage at an integrated circuit, applying an optimal back bias voltage to a voltage reduction circuit that is formed in an isolation well when the external voltage reaches a predetermined threshold value, and reducing the external voltage with the voltage reduction circuit.